The CPU is the heart of a computer for executing command and other versatile function. To simplify layout, a controller chip is provided as interface between the CPU and memory (such as DRAM), accelerated graphic port (AGP) and other peripherals. The controller chip generally comprises FIFO (first-in first-out) queues to temporarily store the requests from the CPU and the controller chip manages the FIFO queues for efficiency operation of the computer system.
FIG. 1 shows a block diagram illustrating the arrangement of a prior art controller chip. The controller chip 6 is connected between a CPU 1 and a DRAM unit 2. The controller chip 6 is composed of a write queue 5, a read queue 4 and an arbiter 3. The write requests of the CPU 1 for accessing the DRAM unit 2 are firstly stored in the write queue 5 and the read requests of the CPU 1 for accessing the DRAM unit 2 are firstly stored in the read queue 4. The arbiter 3 is coupled between the write queue 5 (the read queue 4) and the DRAM unit 2 and controls the transmission of the requests stored in the write queue 5 (the read queue 4) to the DRAM unit 2 for regulating the transaction between the CPU 1 and the DRAM unit 2.
In conventional computer, the CPU 1 has a host bus with bandwidth less than the bandwidth of the memory bus. In case that the CPU 1 sends a plurality of requests to the DRAM unit 2, a host bandwidth limited case is encountered wherein the host bus bandwidth is congested and the memory bus bandwidth is sufficient. To exploit fully ability of the CPU 1, the scheduler in the arbiter 3 processes read requests with higher priority in host bandwidth limited case. The read requests are dominant such that the CPU 1 will rapidly fetch required data for efficient processing.
On the other hand, the write requests are firstly stored in the write queue 5 and the arbiter 3 will halt the write requests until the accumulated number of the write requests exceeds a predetermined value. Therefore, the overall efficiency of the computer system can be enhanced.
In present computer system, the host bus has bandwidth larger than the bandwidth of the memory bus. Therefore, the computer system is operated in a DRAM bandwidth limited case, especially when the CPU 1 has sent many requests to the DRAM unit 2 and the bus bandwidth of the DRAM unit 2 is occupied by the requests of the CPU 1. The scheduler in the arbiter 3 should have more sophisticated strategy to prevent efficiency degrade of the computer system.